Search - frequency divider

[VHDL-FPGA-Verilog] fdivision

Description: 用verilog编写适中分频器并且还有测试程序-verilog prepared with moderate frequency divider and another test procedures
Platform: | Size: 25600 | Author: | Hits:

[Software Engineering] fenpinqi

Description: 《分频器设计》绝对好用的EDA实验程序！已经通过测试。VHDL语言编写-"Frequency Divider" absolutely good for EDA experimental procedure! Already passed the test. VHDL language
Platform: | Size: 1024 | Author: 潘晓峰 | Hits:

[assembly language] cpld

Description: 一个好用的整数分频电路保证你喜欢能够实现对任意整数的分频电路设计-a handy integer frequency divider circuit assures you like to be able to achieve arbitrary integer frequency circuit design
Platform: | Size: 1024 | Author: 王多奎 | Hits:

[RFID] dpll

Description: DPLL由鉴相器模K加减计数器脉冲加减电路同步建立侦察电路模N分频器构成. 整个系统的中心频率(即signal_in和signal_out的码速率的2倍) 为clk/8/N. 模K加减计数器的K值决定DPLL的精度和同步建立时间,K越大,则同步建立时间长,同步精度高.反之则短,低.-DPLL phase detector by the addition and subtraction counter modulus K synchronous pulse addition and subtraction circuit detection circuit establishing mode N divider constituted. The entire system of the center frequency (ie signal_in and signal_out the code rate of 2 times) for clk/8/N. Modulus K addition and subtraction of the K value of Counter DPLL decision accuracy and synchronization set-up time, K the greater the synchronization set-up time is long, synchronous and high accuracy. In contrast the short and low.
Platform: | Size: 1024 | Author: | Hits:

[VHDL-FPGA-Verilog] freqdivfinal

Description: 用vhdl实现的分频器，可产生任意对主时钟的分频，从而是实现不同频率pwm的控制-Achieved using VHDL divider can produce any of the sub-master clock frequency, thereby achieving different frequency pwm control
Platform: | Size: 2048 | Author: | Hits:

[VHDL-FPGA-Verilog] divide

Description:
Platform: | Size: 17408 | Author: linew | Hits:

[VHDL-FPGA-Verilog] fpga-fredivn

Description:
Platform: | Size: 2048 | Author: libing | Hits:

[VHDL-FPGA-Verilog] divider

Description: 该模块为分频器，将1KHZ的时钟频率分频成每分钟一次的时钟频率事实上，该源码可以实现任意整数的分频，主要让N的值设置好相应的数字-The module for the divider, the clock frequency 1KHz frequency per minute into the first clock frequency In fact, the source can be any integer frequency, mainly to allow the value of N is set up the corresponding figure
Platform: | Size: 1024 | Author: Tomy Lee | Hits:

[Embeded-SCM Develop] divp5

Description: fpga上实现的最小是0.5分频的任意分频器-FPGA to achieve the minimum 0.5 hours are arbitrary frequency divider
Platform: | Size: 1024 | Author: 王石子 | Hits:

[VHDL-FPGA-Verilog] FPQ

Description: 分频器的vhdl描述，在源代码中完成对时钟信号CLK的2分频,4分频,8分频,16分频-Divider vhdl description of the source code at the completion of the CLK clock signal frequency of 2 hours, 4 minutes frequency, frequency of 8 hours, 16 minutes frequency
Platform: | Size: 1024 | Author: LS | Hits:

[VHDL-FPGA-Verilog] FPGA_nCLK

Description: VHDL语言的高频时钟分频模块。一种新的分频器实现方法。-VHDL language at the high-frequency clock frequency modules. Divider to achieve a new method.
Platform: | Size: 49152 | Author: 李超 | Hits:

[VHDL-FPGA-Verilog] VHDL_procedures

Description: VHDL程序来让蜂鸣器发出音乐的声音这种电路设计要分好几个模块主要思路是用ROM记录乐谱然后用分频器分频还有就是用计数器读取乐谱另外还可以扩展使其显示音符这是一个做好了的就是ROM没填谱-VHDL procedures are in place to allow the voice of music The buzzer sounded a circuit design that several sub-modules to the main idea is to record music with ROM and then use the frequency divider is also counter to read music to use can be extended also to show notes This is a good ROM没填spectrum is
Platform: | Size: 2048 | Author: yy0838 | Hits:

[Windows Develop] DVF

Description: 数控分频器的设计数控分频器端口定义： CLK：时钟输入 D[7..0]：预置数据 Fout：分频输出说明： D[7..0]作为8位加1计数器的初值，初值越大，分频输出频率越高，反之越低， -NC NC divider divider port the definition of design: CLK: Clock input D [7 .. 0]: preset data Fout: frequency output that: D [7 .. 0] as 8-bit counter plus 1 the initial value, the greater the initial value, the higher the output frequency divider, on the contrary the lower the
Platform: | Size: 1024 | Author: 张娟 | Hits:

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[VHDL-FPGA-Verilog] fdivision

[Software Engineering] fenpinqi

[assembly language] cpld

[RFID] dpll

[VHDL-FPGA-Verilog] freqdivfinal

[VHDL-FPGA-Verilog] divide

[VHDL-FPGA-Verilog] fpga-fredivn

[VHDL-FPGA-Verilog] divider

[Embeded-SCM Develop] divp5

[VHDL-FPGA-Verilog] FPQ

[VHDL-FPGA-Verilog] FPGA_nCLK

[VHDL-FPGA-Verilog] VHDL_procedures

[Windows Develop] DVF

[Other] mod_m_counter

[VHDL-FPGA-Verilog] Frequency_Divider_VhdlCode

[VHDL-FPGA-Verilog] FPQ

[VHDL-FPGA-Verilog] Freq_Divider

[VHDL-FPGA-Verilog] verilogfenpinqi

[VHDL-FPGA-Verilog] chengxu

[VHDL-FPGA-Verilog] Frequencydivider

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